1. Field of the Invention
The present invention relates to a bus arbiter and a bus access arbitrating method.
2. Description of the Related Art
Conventionally, a processor is known in which a plurality of masters and a plurality of slaves are connected with a bus such as a CPU local bus and a PCI bus. In such a processor, when the masters generate bus access requests to the slaves at a same time, a competition of the bus accesses requests is caused. The processor is provided with a bus arbiter to avoid the competition of the bus access requests. The bus arbiter arbitrates the bus access requests from the plurality of masters and allocates a bus usage right to only one of the masters.
Hereinafter, the conventional bus arbiter will be described. FIG. 1 is a block diagram showing the structure of the conventional processor to which the bus arbiter is applied.
Referring to FIG. 1, the processor is composed of a bus 10, a plurality of masters (MASTER1 to MASTERn) 201 to 20n which can access the bus 10 actively, a plurality of slaves (SLAVE1 to SLAVEm) 301 to 30m which receive the access passively, and a bus arbiter (ARBITER) 40. It should be noted that in case of a PCI local bus or Card Bus (Card Bus), the slave is called a target, too.
Generally, the masters 201 to 20n generate bus access requests asynchronously. The bus arbiter 40 arbitrates the competition of the bus access requests asynchronously generated. The masters 201 to 20n send the bus access requests REQ1 to REQn to the bus arbiter 40 to request the bus usage right. The bus arbiter 40 determines one of the masters for the bus usage right to be allocated in response to the bus access requests REQ1 to REQn and sends one of bus use permission signals GNT1 to GNTn corresponding to the master, to which the bus usage right is allocated, to permit the use of the bus 10.
FIG. 2 is a block diagram showing the detailed structure of the bus arbiter 40. The bus arbiter 40 is composed of an arbitration priority control section (PRICONT) 50, a plurality of arbitration priority generating sections (PRIGEN1 to PRIGENn) 511 to 51n, an arbitration priority comparing section (CMPR) 52, an arbitration result notifying section (GNTGEN) 53, and a bus monitoring section (BUSCHK) 54.
When the bus access requests REQ1 to REQn are sent from the masters 201 to 20n to the bus arbiter 40, a bus access arbitration process is started. In the bus access arbitration process, the arbitration priority generating section PRIGENi 51i (i=1, 2, . . . , n, hereinafter, being same) receives the bus access request REQi, and generates arbitration priority data PRIINFOi based on basic priority data PRIBASEi which is sent as a basic priority from the arbitration priority control section 50. Also, the arbitration priority generating section PRIGENi 51i generates a request ON signal REQONi showing the existence or non-existence of the bus access request REQi from the master 20i. The arbitration priority data PRIINFOi and the request ON signal REQONi are sent to the arbitration priority comparing section 52.
The arbitration priority comparing section 52 compares the arbitration priority data to select the master with the highest arbitration priority from among the masters corresponding to the request ON signals. The arbitration priority comparing section 52 sends an arbitration priority comparison resultant signal to the arbitration result notifying section 53 based on the comparing result. The arbitration priority comparison resultant signal contains data to specify the selected master. The arbitration result notifying section 53 sends a bus usage permission signal GNTi to the selected master 20i shown by the arbitration priority comparison resultant signal.
The above-mentioned bus access arbitration process is carried out for every bus access, i.e., for every bus cycle. The bus monitoring section 54 monitors and detects the start and end of the bus cycle, and sends a bus arbitration control request signal to the arbitration priority control section 50 and the arbitration priority comparing section 52, to define the timing to permit the use of the bus 10 in the next bus cycle.
Also, the arbitration result notifying section 53 sends to the arbitration priority control section 50 an arbitration result reflection control signal generated based on the arbitration priority comparison resultant signal from the arbitration priority comparing section 52 to reflect an arbitration result. By this, the arbitration priority control section 50 can reflect the arbitration result to the generation of the next basic priority data PRIBASEi.
FIG. 3 is a block diagram showing the arbitration priority generating section (PRIGENn) 51n, the arbitration priority comparing section (CMPR) 52 and arbitration result notifying section (GNTGEN) 53 in detail. It should be noted that each structure of the arbitration priority generating section (PRIGEN1 to PRIGENn−1) 511 to 51n−1 are omitted from FIG. 3. However, they have the same structure as that of the arbitration priority generating section (PRIGENn) 51n. 
The arbitration priority generating section 51i generates the arbitration priority data PRIINFOi based on the basic priority data PRIBASEi from the arbitration priority control section 50, and the arbitration priority data PRIINFOi contains a plurality of bits showing a priority. Also, the arbitration priority generating section 51i generates the request ON signal REQONi based on the bus access request REQi to show the existence or non-existence of the bus access request. The arbitration priority data PRIINFOi and the request ON signal REQONi are sent to the arbitration priority comparing section 52 as different parameters.
The arbitration priority comparing section 52 is composed of an arbitration object determining section 70. The arbitration object determining section 70 determines as comparison objects, only the arbitration priority data corresponding to the request ON signals and outputted from the arbitration priority generating sections. The arbitration priority comparing section 52 selects the highest one of the arbitration priority data determined as the comparison objects by the arbitration object determining section 70, and sends the arbitration priority comparison resultant signal to the arbitration result notifying section 53. The arbitration result notifying section 53 generates and sends the bus usage permission signal to the master with the highest priority based on the arbitration priority comparison resultant signal to permit the bus use. Thus, the bus access arbitration process completes.
As mentioned above, in the conventional bus arbiter, when the bus access requests are generated, the request ON signals are sent to the arbitration priority comparing section in addition to the arbitration priorities, to show the existence or non-existence of a bus access request. The arbitration priority comparing section 52 includes the arbitration object determining section 70, and determines whether each bus access request is the object of the arbitration, based on the request ON signal by the arbitration object determining section 70. Therefore, the arbitration priority comparing section 52 becomes larger in the hardware structure. As a result, the bus arbiter becomes expensive.
In conjunction with the above description, a bus control apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-170255). In the bus control apparatus of this conventional example, a plurality of processors are connected with a bus. A selector selects one of the plurality of processors. A priority determining section determines priorities of the processors dynamically based on the statuses of them.
Also, a bus arbiter is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-242021). In the bus arbitration circuit of this conventional example, the priority of each of a plurality of masters to the bus usage right is stored in a priority storage circuit. A priority comparing circuit compares the priorities stored in the priority storage circuit to determine the current priority order of the masters to bus usage right. A bus use permission signal is outputted to one of the masters, which has the highest priority of the current priority order, by the priority comparing circuit in response to bus use requests. A priority control circuit carries out a priority control to increase the priorities stored in the priority storage circuit and corresponding to the masters other than the master with the highest priority. Also, the priority of the master with the highest priority is decreased. By the structure, it is possible to equally allocate the bus usage right to masters without limiting the reception of the bus use requests. Also, it is possible to allocate the bus usage right to the masters with high priority levels and the masters with low priority levels while keeping a constant rate.
Also, a bus arbiter circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-274254). In the bus arbiter circuit of this conventional example, a bus use permission signal generating section receives a bus use request from a plurality of masters and allocates a bus use permission signal to a master with the highest priority. A bus use priority updating section reduces the priority of the master with the bus use permission signal to the lowest. Thus, the priorities of the masters with the priorities lower than the master supplied with the bus use permission signal are made higher by one. As a result, the bus use permission can be given to the plurality of masters equally.
Also, a bus control system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-243093). In the bus control system for a serial bus of this conventional example, a plurality of bus masters are connected with a bus. Each bus master is composed of a bus request priority setting section which sets priority of a bus request variably, and a priority sending section which sends priority data indicative of the priority onto the bus. A priority receiving section receives the priority data from the bus masters. A bus arbiter permits the bus requests to the bus masters in accordance with a higher order of the priorities received by the priority receiving section.
Also, a method of determining a circulating-type bus priority is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-249000). In the bus arbitration method for a serial bus of this conventional example, when a plurality of ports connected with the serial bus tries to acquire the bus, one of the plurality of ports is selected, and the bus is allocated to the selected port. That is, when transmission requests are outputted from the plurality of ports to the bus, one of the plurality of ports having the largest port identification number is selected to acquire the bus, and the port identification number of the port having acquired the bus is made smaller than the port identification numbers of the other ports.
Also, a common bus usage right control system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-161257). In the common bus usage right control system of this conventional example, a plurality of bus masters are connected with a common bus. An allocating section allocates a priority level to each of use requests of the common bus from the plurality of bus masters in accordance with an external instruction. An arbitration section arbitrates the use requests to the common bus in accordance with the priority levels. A connection section is provided to connect the plurality of bus masters in series such that a bus use permission signal is propagated between ones of the plurality of bus masters to which the same priority level is allocated.
Also, a bus arbitration system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-228446). The bus arbitration system of this conventional example is composed of a bus arbitration circuit to arbitrate accesses to a bus from a plurality of bus masters. Each bus the master has a function to output a bus use request, a function to wait the bus access until a bus use permission signal is received, and a function to send out an address to the bus. The bus arbitration circuit is composed of a priority data storage section for storing a plurality of sets of bus master priority data, and each set of bus master priority data shows priorities of the bus masters. A priority data selecting section selects one of the plurality of sets one by one for every bus cycle. A bus use permission signal generating circuit outputs a bus use permission signal to one with the highest priority of the bus masters which have generated bus use requests in accordance with the selected set of bus master priority data, to permit the use of the bus during only one bus cycle bus.
Also, a bus arbitration apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-254823). In this conventional example, a plurality of devices are connected to a bus. The bus arbitration apparatus arbitrates the bus use requests when the bus use requests are outputted from the plurality of devices and compete to each other. The bus arbitration apparatus stores variable weight values which are different between the devices and are changed for every bus arbitration. The variable weight values are used as the priorities of the devices.
Also, a first arrival priority bus competition control system is disclosed in Japanese Laid Open Patent Application (JP-P2000-99455A). In this conventional example, a plurality of input/output processors are connected to a bus. A first arrival fixed priority arbitration section selects one of bus use request signals in accordance with the arrival order in units of clocks. A change detecting section detects the change of the priority output from the arbitration section. A priority storage section stores the priority output from the change detecting section until the bus use end. A bus use permission signal synchronization section outputs the bus use permission signal. An arbitration control unit controls the bus use permission signal synchronization section based on the output state of the bus use permission signal.